DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 334

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

Port A Open Drain Control Register (PAODR) (On-Chip ROM Version Only)
Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390.
PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each port A pin (PA
All bits are valid in mode 7.
Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output, while clearing the bit to 0
makes the pin a CMOS output.
PAODR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
9.8.3
Mode 7 (On-Chip ROM Version Only): In mode 7, port A pins function as I/O ports and interrupt input pins. Input or
output can be specified for each pin on an individual bit basis. Setting a PADDR bit to 1 makes the corresponding port A
pin an output port, while clearing the bit to 0 makes the pin an input port.
Port A pin functions in mode 7 are shown in figure 9-8.
Rev.6.00 Oct.28.2004 page 304 of 1016
REJ09B0138-0600H
Bit
Initial value :
R/W
Pin Functions
:
:
PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR
R/W
7
0
R/W
6
0
Figure 9-8 Port A Pin Functions (Mode 7)
R/W
5
0
Port A
R/W
4
0
PA
PA
PA
PA
PA
PA
PA
PA
R/W
3
0
7
6
5
4
3
2
1
0
(I/O)/IRQ7 (input)
(I/O)/IRQ6 (input)
(I/O)/IRQ5 (input)
(I/O)/IRQ4 (input)
(I/O)
(I/O)
(I/O)
(I/O)
R/W
2
0
R/W
1
0
R/W
0
0
7
to PA
0
).