DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 401

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

10.4
10.4.1
Operation in each mode is outlined below.
Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, synchronous counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs
synchronous presetting. That is, when TCNT for a channel designated for synchronous operation is rewritten, the TCNT
counters for the other channels are also rewritten at the same time. Synchronous clearing of the TCNT counters is also
possible by setting the timer synchronization bits in TSYR for channels designated for synchronous operation.
Buffer Operation
Cascaded Operation: The channel 1 counter (TCNT1), channel 2 counter (TCNT2), channel 4 counter (TCNT4), and
channel 5 counter (TCNT5) can be connected together to operate as a 32-bit counter.
PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of TIOR. A PWM
waveform with a duty of between 0% and 100% can be output, according to the setting of each TGR register.
Phase Counting Mode: In this mode, TCNT is incremented or decremented by detecting the phases of two clocks input
from the external clock input pins in channels 1, 2, 4, and 5. When phase counting mode is set, the corresponding TCLK
pin functions as the clock pin, and TCNT performs up- or down-counting.
This can be used for two-phase encoder pulse input.
When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the relevant channel is transferred to TGR.
When TGR is an input capture register
When input capture occurs, the value in TCNT is transfer to TGR and the value previously held in TGR is transferred
to the buffer register.
Operation
Overview
Rev.6.00 Oct.28.2004 page 371 of 1016
REJ09B0138-0600H