DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 669

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated
more than (N) times on the same bits.
Note: Use a (z3) s write pulse for additional
Note: 7 Write Pulse Width
Number of Writes (n)
Additional program data
Write pulse application subroutine
Reprogram data area
Wait (z1) s or (z2) s or (z3) s
Program data area
area (128 bytes)
Clear PSU bit in FLMCR1
programming.
Set PSU bit in FLMCR1
Sub-routine write pulse
Clear P bit in FLMCR1
(128 bytes)
(128 bytes)
1000
Set P bit in FLMCR1
998
999
10
11
12
13
1
2
3
4
5
6
7
8
9
.
.
.
RAM
Disable WDT
Enable WDT
Wait (y) s
Wait ( ) s
Wait ( ) s
End sub
Write Time (z) s
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be
Figure 19-48 Program/Program-Verify Flowchart
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
.
.
.
2. Verify data is read in 16-bit (W) units.
3. Even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programming if they fail the
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data should
5. A write pulse of (z1) or (z2)
6. For the values of x, y, z1, z2, z3, , , , , , , and N, see section 22.3.6, the Flash Memory Characteristics.
Program Data Operation Chart
Additional Program Data Operation Chart
Reprogram Data (X')
performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
subsequent verify operation.
be provided in RAM. The contents of the reprogram data and additional program data areas are modified as programming proceeds.
program data is programmed, a write pulse of (z3)
been applied.
*6
*5*6
*6
*6
Original Data (D)
0
1
0
1
Increment address
Verify Data (V)
Verify Data (V)
s
0
1
0
1
0
1
0
1
should be applied according to the progress of programming. See note 7 for the pulse widths. When the additional
NG
Store 128-byte program data in program
data area consecutively to flash memory
additional program data area in RAM to
Write 128-byte data in RAM reprogram
Additional Program Data (Y)
Transfer reprogram data to reprogram
Additional program data computation
H'FF dummy write to verify address
data area and reprogram data area
Transfer additional program data to
Sequentially write 128-byte data in
Reprogram Data (X)
additional program data area
Reprogram data computation
(z3 s additional write pulse)
Clear SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set SWE bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
End of programming
Read data = verify
(z1) s or (z2) s
Read verify data
data verification
s
flash memory
Write Pulse
should be applied. Reprogram data X' stands for reprogram data to which a write pulse has
Wait (x) s
Wait ( ) s
Wait ( ) s
completed?
Wait (
1
0
1
0
1
Write pulse
Wait (
data area
128-byte
m = 0?
m = 0
6
6
n = 1
data?
Start
n ?
n ?
OK
OK
OK
OK
OK
s
s
Sub-routine-call
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Additional programming executed
Additional programming not executed
Additional programming not executed
Additional programming not executed
NG
NG
NG
NG
*6
*6
*4
*1
See note 7 regarding pulse width
switching.
*6
*6
*6
*2
*4
*3
*4
*6
*1
*6
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
m = 1
Clear SWE bit in FLMCR1
Comments
Comments
Programming failure
Wait (
n
Rev.6.00 Oct.28.2004 page 639 of 1016
N?
OK
s
NG
n
n + 1
*6
REJ09B0138-0600H