DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 253

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

Figure 7-24 shows an example of DREQ pin falling edge activated block transfer mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write
cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in
the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling
for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA dead cycle ends,
acceptance resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this operation is
repeated until the transfer ends.
Figure 7-24 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer
[1]
[2] [5]
[3] [6]
[4] [7]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Address bus
DMA control
Channel
DREQ
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of ø,
and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
Start of DMA cycle; DREQ pin high level sampling on the rising edge of ø starts.
When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.)
ø
Bus release
Minimun of 2 cycles
[1]
Request
Idle
[2]
Read
Request clear period
[3]
Transfer
DMA
read
source
Write
1 block transfer
Acceptance resumes
DMA
write
destination
Transfer
Dead
Minimun of 2 cycles
[4]
Request
DMA
dead
Idle
[5]
release
Bus
Read
[6]
Request clear period
Transfer
DMA
source
read
Write
1 block transfer
Rev.6.00 Oct.28.2004 page 223 of 1016
destination
Transfer
DMA
write
Dead
Acceptance resumes
DMA
dead
[7]
Idle
release
Bus
REJ09B0138-0600H