DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 666

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved
for use by the boot program, as shown in figure 19-46. The area to which the programming control program is transferred
is H'FFE400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into
RAM enters the execution state. A stack area should be set up as required.
Notes on Use of Boot Mode
Rev.6.00 Oct.28.2004 page 636 of 1016
REJ09B0138-0600H
When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI’s RxD1 pin.
The reset should end with RxD1 high. After the reset ends, it takes approximately 100 states before the chip is ready to
measure the low-level period of the RxD1 pin.
In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks
are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming
is performed, or if the program activated in user program mode is accidentally erased.
Interrupts cannot be used while the flash memory is being programmed or erased.
The RxD1 and TxD1 pins should be pulled up on the board.
Before branching to the programming control program (RAM area H'FFE400 to H'FFFBFF), the chip terminates
transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the
adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state
(P31DDR = 1, P31DR = 1).
The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized
immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used
implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program.
Initial settings must also be made for the other on-chip registers.
Boot mode can be entered by making the pin settings shown in table 19-35 and executing a reset-start.
Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the mode pins, and
executing reset release*
Note: * The boot program area cannot be used until a transition is made to the execution state
for the programming control program transferred to RAM. Note that the boot program
remains stored in this area after a branch is made to the programming control program.
1
. Boot mode can also be cleared by a WDT overflow reset.
Figure 19-46 RAM Areas in Boot Mode
H'FFDC00
H'FFE3FF
H'FFFBFF
control program
Boot program
Programming
(2 kbytes)
(6 kbytes)
area*
area