DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 446
![IC H8S MCU FLASH 256K 120TQFP](/photos/28/61/286120/120-tqfp_sml.jpg)
DF2398TE20
Manufacturer Part Number
DF2398TE20
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2398TE20
HD64F2398TE20
HD64F2398TE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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11.2.2
Note: * A bit that has been set for pulse output by NDER is read-only.
PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse output.
11.2.3
NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output. During pulse output, the
contents of NDRH and NDRL are transferred to the corresponding bits in PODRH and PODRL when the TPU compare
match event specified by PCR occurs. The NDRH and NDRL addresses differ depending on whether pulse output groups
have the same output trigger or different output triggers. For details see section 11.2.4, Notes on NDR Access.
NDRH and NDRL are each initialized to H'00 by a reset and in hardware standby mode. They are not initialized in
software standby mode.
11.2.4
The NDRH and NDRL addresses differ depending on whether pulse output groups have the same output trigger or
different output triggers.
Same Trigger for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by the same compare match event,
the NDRH address is H'FF4C. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FF4E
consists entirely of reserved bits that cannot be modified and are always read as 1.
Address H'FF4C
Rev.6.00 Oct.28.2004 page 416 of 1016
REJ09B0138-0600H
PODRH
Bit
Initial value :
R/W
PODRL
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Output Data Registers H and L (PODRH, PODRL)
Next Data Registers H and L (NDRH, NDRL)
Notes on NDR Access
:
:
:
:
:
:
POD15
NDR15
R/(W)*
R/(W)*
POD7
R/W
7
0
7
0
7
0
POD14
NDR14
R/(W)*
R/(W)*
POD6
R/W
6
0
6
0
6
0
POD13
NDR13
R/(W)*
R/(W)*
POD5
R/W
5
0
5
0
5
0
POD12
NDR12
R/(W)*
R/(W)*
POD4
R/W
4
0
4
0
4
0
POD11
NDR11
R/(W)*
R/(W)*
POD3
R/W
3
0
3
0
3
0
POD10
NDR10
R/(W)*
R/(W)*
POD2
R/W
2
0
2
0
2
0
R/(W)*
R/(W)*
POD9
POD1
NDR9
R/W
1
0
1
0
1
0
R/(W)*
R/(W)*
POD8
POD0
NDR8
R/W
0
0
0
0
0
0
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