DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 281

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

8.3.2
The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be
directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation
source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0.
At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or
corresponding DTCER bit is cleared. Table 8-3 shows activation source and DTCER clearance. The activation source flag,
in the case of RXI0, for example, is the RDRF flag of SCI0.
Table 8-3
Figure 8-3 shows a block diagram of activation source control. For details see section 5, Interrupt Controller.
When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller
priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with
the default priorities.
Activation Sources
Activation Source
Software activation The SWDTE bit is cleared to 0
Interrupt activation
Activation Source and DTCER Clearance
Source flag cleared
IRQ interrupt
supporting
DTVECR
On-chip
module
Figure 8-3 Block Diagram of DTC Activation Source Control
When the DISEL Bit Is 0 and
the Specified Number of
Transfers Have Not Ended
The corresponding DTCER bit
remains set to 1
The activation source flag is
cleared to 0
Interrupt
request
DTCER
Select
Clear
Interrupt controller
controller
Clear
DTC
When the DISEL Bit Is 1, or when
the Specified Number of Transfers
Have Ended
The SWDTE bit remains set to 1
An interrupt is issued to the CPU
The corresponding DTCER bit is cleared
to 0
The activation source flag remains set to 1
A request is issued to the CPU for the
activation source interrupt
Clear request
Interrupt mask
Rev.6.00 Oct.28.2004 page 251 of 1016
CPU
REJ09B0138-0600H