DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 131

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

5.6.2
Figure 5-9 shows a block diagram of the DTC and DMAC interrupt controller.
5.6.3
The interrupt controller has three main functions in DTC and DMAC control.
Selection of Interrupt Source: With the DMAC, the activation source is input directly to each channel. The activation
source for each DMAC channel is selected with bits DTF3 to DTF0 in DMACR. Whether the selected activation source is
to be managed by the DMAC can be selected with the DTA bit of DMABCR. When the DTA bit is set to 1, the interrupt
source constituting that DMAC activation source is not a DTC activation source or CPU interrupt source.
For interrupt sources other than interrupts managed by the DMAC, it is possible to select DTC activation request or CPU
interrupt request with the DTCE bit of DTCERA to DTCERF in the DTC.
After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with
the specification of the DISEL bit of MRB in the DTC.
When the DTC has performed the specified number of data transfers and the transfer counter value is zero, the DTCE bit
is cleared to 0 and an interrupt request is sent to the CPU after the DTC data transfer.
Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not
affected by mask or priority levels. See section 7.6, Interrupts, and section 8.3.3, DTC Vector Table, for the respective
priorities.
With the DMAC, the activation source is input directly to each channel.
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data
transfer is performed first, followed by CPU interrupt exception handling.
Block Diagram
Operation
supporting
On-chip
interrupt
module
IRQ
Interrupt source
clear signal
Figure 5-9 Interrupt Control for DTC and DMAC
Interrupt
request
Interrupt controller
Selection
DTVECR
DTCER
circuit
Select
signal
Clear signal
SWDTE
clear signal
DMAC
Determination of
Control logic
priority
Rev.6.00 Oct.28.2004 page 101 of 1016
CPU interrupt
request vector
number
DTC activation
request vector
number
Clear signal
I, I2 to I0
CPU
DTC
REJ09B0138-0600H