HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1018

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 28
28.4
The D/A converter incorporates two D/A channels that can operate individually.
The D/A converter executes D/A conversion while analog output is enabled by the D/A control
register (DACR). If the D/A data registers (DADR0 and DADR1) are modified, the D/A converter
immediately initiates the new data conversion. When the DAOE1 and DAOE0 bits in the DACR
register are set to 1, D/A conversion results are output.
An example of D/A conversion for channel 0 is shown below. The operation timing is shown in
figure 28.2.
1. Write conversion data to DADR0.
2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. The results are output after
3. When D/A data register 0 (DMDR0) is modified, the conversion starts again.
4. When the DAOE0 bit is cleared to 0, analog output is disabled (high-impedance state).
Rev. 3.00 Jan. 18, 2008 Page 956 of 1458
REJ09B0033-0300
the conversion has ended. The output value will be (DADR0 contents/256) × AVcc.
The conversion results are output continuously until DADR0 is modified or the DAOE0 bit is
cleared to 0.
The results are output after the conversion has ended.
Address bus
Operation
DADR0
DAOE0
D/A Converter (DAC)
[Legend]
t
DCONV
DA0
Pφ
: D/A conversion time
write cycle
DADR0
High impedance
state
Figure 28.2
write cycle
DACR
t
DCONV
Conversion data (1)
D/A Converter Operation Example
Conversion result (1)
write cycle
DADR0
t
DCONV
Conversion data (2)
Conversion
result (2)
write cycle
DACR