HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 314

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8
8.3.4
IRR0 is an 8-bit register that indicates interrupt requests from the TMU and IRQ0 to IRQ5.
Rev. 3.00 Jan. 18, 2008 Page 252 of 1458
REJ09B0033-0300
Bit
7
6
5
4
3
2
1
0
Bit Name

TMU_
SUNIR
IRQ5R
IRQ4R
IRQ3R
IRQ2R
IRQ1R
IRQ0R
Interrupt Request Register 0 (IRR0)
Interrupt Controller (INTC)
Initial
Value
0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
TMU_SUNI Interrupt Request
Indicates whether the TMU_SUNI (TMU) interrupt request
is generated.
0: TMU_SUNI interrupt request is not generated
1: TMU_SUNI interrupt request is generated
IRQn Interrupt Request
Indicates whether there is interrupt request input to the
IRQn pin. When edge-detection mode is set for IRQn, an
interrupt request is cleared by writing 0 to the IRQnR bit
after reading IRQnR = 1.
When level-detection mode is set for IRQn, these bits
indicate whether an interrupt request is input. The
interrupt request is set/cleared by only 1/0 input to the
IRQn pin.
IRQnR
0: No interrupt request input to IRQn pin
1: Interrupt request input to IRQn pin
[Legend] n = 0 to 5