HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 938

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 26
26.3.6
When a DSTN panel is used, LDSARL specifies the fetch start address for the lower side of the
panel.
Rev. 3.00 Jan. 18, 2008 Page 876 of 1458
REJ09B0033-0300
Bit
31 to 28 
27, 26
25 to 4
3 to 0
LCDC Start Address Register for Lower Display Data Fetch (LDSARL)
Bit Name Initial Value
SAL25 to
SAL4
LCD Controller (LCDC)
All 0
All 1
All 0
All 0
R/W
R
R
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
These bits are always read as 1. The write value
should always be 1.
Start Address for Lower Panel Display Data Fetch
The start address for data fetch of the display data
must be set within the synchronous DRAM area of
area 3.
STN and TFT: Cannot be used
DSTN: Start address for fetching display data
corresponding to the lower panel
Reserved
These bits are always read as 0. The write value
should always be 0.

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