HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1183

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
31 to 22
21
20
19 to 16
15
14
Bit Name

BASMA
BASMB

SCMFCA
SCMFCB
Initial
Value
All 0
0
0
All 0
0
0
R/W
R
R/W
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Break ASID Mask A
Specifies whether bits in channel A break ASID7 to
ASID0 (BASA7 to BASA0) which are set in BASRA
are masked or not.
0: All BASRA bits are included in the break conditions
1: All BASRA bits are not included in the break
Break ASID Mask B
Specifies whether bits in channel B break ASID7 to
ASID0 (BASB7 to BASB0) which are set in BASRB
are masked or not.
0: All BASRB bits are included in the break conditions
1: All BASRB bits are not included in the break
Reserved
These bits are always read as 0. The write value
should always be 0.
L Bus Cycle Condition Match Flag A
When the L bus cycle condition in the break conditions
set for channel A is satisfied, this flag is set to 1. In
order to clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel A does not
1: The L bus cycle condition for channel A matches
L Bus Cycle Condition Match Flag B
When the L bus cycle condition in the break conditions
set for channel B is satisfied, this flag is set to 1. In
order to clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel B does not
1: The L bus cycle condition for channel B matches
match
and the ASID is checked
conditions and the ASID is not checked
and the ASID is checked
conditions and the ASID is not checked
match
Rev. 3.00 Jan. 18, 2008 Page 1121 of 1458
Section 33 User Break Controller (UBC)
REJ09B0033-0300