HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 763

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

21.3.9
SIFCTR is a 16-bit readable/writable register that indicates the area available for the
transmit/receive FIFO transfer.
Bit
15
14
13
12
11
10
9
8
Bit Name
TFWM2
TFWM1
TFWM0
TFUA4
TFUA3
TFUA2
TFUA1
TFUA0
FIFO Control Register (SIFCTR)
Initial
Value
0
0
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
R
Description
Transmit FIFO Watermark
000: Issue a transfer request when 16 stages of the
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 12 or more stages of
101: Issue a transfer request when 8 or more stages of
110: Issue a transfer request when 4 or more stages of
111: Issue a transfer request when 1 or more stages of
•
•
Transmit FIFO Usable Area
Indicate the number of words that can be transferred by
the CPU or DMAC as B'00000 (full) to B'10000 (empty).
A transfer request to the transmit FIFO is issued by
the TDREQ bit in SISTR.
The transmit FIFO is always used as 16 stages of the
FIFO regardless of these bit settings.
transmit FIFO are empty.
the transmit FIFO are empty.
the transmit FIFO are empty.
the transmit FIFO are empty.
transmit FIFO are empty.
Rev. 3.00 Jan. 18, 2008 Page 701 of 1458
Section 21
Serial I/O with FIFO (SIOF)
REJ09B0033-0300