HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 876

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25
Rev. 3.00 Jan. 18, 2008 Page 814 of 1458
REJ09B0033-0300
Bit
2
1
0
Bit Name
EP5 TS
EP4 TF
EP4 TS
USB Function Controller (USBF)
Initial Value
0
0
0
R/W Description
R/W EP5 (Isochronous-in) Normal Transmission
R/W EP4 (Isochronous-out) Abnormal Reception
R/W EP4 (Isochronous-out) Normal Reception
Flag indicating the FIFO state of EP5.
After the SOF packet is received, the FIFO buffer is
switched automatically. The FIFO buffer which has
transmitted data to the host in the previous frame
(before SOF reception) can be written to by the CPU.
This bit indicates the transmit state in the previous
frame.
[Setting condition]
When a transmission was carried out normally in the
previous frame.
[Clearing conditions]
•
•
Flag indicating the FIFO state of EP4. Indicates the
state of the FIFO buffer that was readable after the
data reception is completed and the next SOF packet
is received.
[Setting condition]
When the transfer data from the host is abnormally
received (packet error) by EP4.
[Clearing conditions]
•
•
Flag indicating the FIFO state of EP4. Indicates the
state of the FIFO buffer that was readable after the
data reception is completed and the next SOF packet
is received.
[Setting condition]
When the transfer data from the host is normally
received by EP4.
[Clearing conditions]
•
•
When reset
When 0 is written to by CPU
When reset
When 0 is written to by CPU
When reset
When 0 is written to by CPU