HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 695

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(6)
Figure 18.16 shows sample flowcharts for simultaneous serial transmission and reception.
Figure 18.16
Data Transfer Operations (Simultaneous Serial Data Transmission and Reception)
Write remaining transmit data to SCFTDR
Set TE and RE bits in SCSCR
simultaneously
When using transmit FIFO data interrupt,
set TIE bit to 1
When using receive FIFO data interrupt,
set RIE bit to 1
Read receive trigger number of receive
Set receive trigger number in RTRG1
Clear TE and RE bits in SCSCR to 0
Read TDFE and RDF bits in SCSSR
SCSSR after reading 1 from them
Write 0 to TDFE and RDF bits in
Sample Simultaneous Serial Transmission and Reception Flowchart (1)
data bytes from SCFRDR
and RTRG0 in SCFCR
transmission/reception
transmission/reception
Start of simultaneous
TDFE =1?
TDFE =1?
Yes
RDF =1?
RDF =1?
End of
(First Transfer after Initialization)
Yes
No
No
Section 18
1
2
3
4
1. Set the receive trigger number
2. Write the remaining transmit data
3. Transmission/reception is started
4. After the end of transmission/reception,
in SCFCR.
to SCFTDR, and if there is receive
data in the FIFO, read receive data
until there is less than the receive
trigger setting number, read the
TDFE and RDF bits in SCSSR, and
if 1, clear to 0.
when the TE and RE bits in SCSCR
are set to 1. The TE and RE bits
must be set simultaneously.
clear the TE and RE bits to 0.
Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Jan. 18, 2008 Page 633 of 1458
REJ09B0033-0300