HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1069

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
30.4.2
Figure 30.2 shows the data format used by the smart card interface. The smart card interface
performs a parity check for each frame during reception.
During reception in T = 0 mode, if a parity error is detected, an error signal is returned to the
transmit side, requesting data retransmission. When the transmit side samples the error signal, it
retransmits the same data.
During reception in T = 1 mode, if a parity error is detected, an error signal is not returned. During
transmission, error signals are not sampled and data is not retransmitted.
The operation sequence is as follows.
1. When not in use, the data line is in a high-impedance state and fixed at high level by a pull-up
2. The transmit side initiates transmission of one frame of data. The data frame begins with the
resistance.
start bit (Ds: low level). This is followed by eight data bits (D0 to D7) and the parity bit (Dp).
Data Format
Figure 30.2
Ds: Start bit, D0 to D7: Data bits, Dp: Parity bit, DE: Error signal
When a parity error occurs in T=1 mode
When a parity error occurs in T=0 mode
When no parity error occurs
Ds
Ds
Ds
Ds
Ds
D0
D0
D0
D1 D2
D1
D1
Data Format Used by Smart Card Interface
Transmitter output
Transmitter output
D2
Transmitter output
D2
D3
D3
D3
D4
D4
D4
D5 D6
D5
D5 D6 D7
D6
Rev. 3.00 Jan. 18, 2008 Page 1007 of 1458
D7 Dp
D7
Dp
Dp
Section 30
Receiver output
DE
SIM Card Module (SIM)
REJ09B0033-0300

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