HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 292

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Exception Handling
(5)
• Conditions
• Types
• Save address
• Exception code
• Remarks
(6)
• Conditions
• Types
• Save address
• Exception code
Rev. 3.00 Jan. 18, 2008 Page 230 of 1458
REJ09B0033-0300
When a break condition set in the user break controller is satisfied
Break (L bus) before instruction execution: Instruction synchronous, re-execution type
Operand break (L bus): Instruction synchronous, processing-completion type
Data break (L bus): Instruction asynchronous, processing-completion type
I bus break: Instruction asynchronous, processing-completion type
Re-execution type: An address of the instruction where a break occurs (a delayed branch
instruction address if an instruction is assigned to a delay slot)
Processing-completion type: An address of the instruction following the instruction where a
break occurs (a delayed branch instruction destination address if an instruction is assigned to a
delay slot)
H'1E0
For details on user break controller, refer to section 33, User Break Controller (UBC).
 Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
 Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n +
Instruction asynchronous, processing-completion type
An address of the instruction following the instruction where a break occurs (a delayed branch
instruction destination address if an instruction is assigned to a delay slot)
H'5C0
User break point trap
DMA address error
3)