HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 15

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

8.4
8.5
Section 9 Bus State Controller (BSC)..................................................................279
9.1
9.2
9.3
9.4
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10 Interrupt Request Register 6 (IRR6) ..................................................................... 259
8.3.11 Interrupt Request Register 7 (IRR7) ..................................................................... 260
8.3.12 Interrupt Request Register 8 (IRR8) ..................................................................... 261
8.3.13 Interrupt Request Register 9 (IRR9) ..................................................................... 262
8.3.14 PINT Interrupt Enable Register (PINTER)........................................................... 264
8.3.15 Interrupt Control Register 2 (ICR2)...................................................................... 265
Interrupt Sources................................................................................................................ 266
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
Operation ........................................................................................................................... 276
8.5.1
8.5.2
Features.............................................................................................................................. 279
Input/Output Pins ............................................................................................................... 283
Area Overview ................................................................................................................... 285
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
Register Descriptions ......................................................................................................... 290
9.4.1
9.4.2
9.4.3
9.4.4
Interrupt Priority Registers A to J (IPRA to IPRJ)................................................ 247
Interrupt Control Register 0 (ICR0)...................................................................... 249
Interrupt Control Register 1 (ICR1)...................................................................... 250
Interrupt Request Register 0 (IRR0) ..................................................................... 252
Interrupt Request Register 1 (IRR1) ..................................................................... 253
Interrupt Request Register 2 (IRR2) ..................................................................... 254
Interrupt Request Register 3 (IRR3) ..................................................................... 255
Interrupt Request Register 4 (IRR4) ..................................................................... 256
Interrupt Request Register 5 (IRR5) ..................................................................... 257
NMI Interrupt........................................................................................................ 266
IRQ Interrupts ....................................................................................................... 266
IRL interrupts........................................................................................................ 267
PINT Interrupts ..................................................................................................... 268
On-Chip Peripheral Module Interrupts ................................................................. 268
Interrupt Exception Handling and Priority............................................................ 269
Interrupt Sequence ................................................................................................ 276
Multiple Interrupts ................................................................................................ 278
Area Division........................................................................................................ 285
Shadow Area......................................................................................................... 285
Address Map ......................................................................................................... 287
Area 0 Memory Type and Memory Bus Width .................................................... 289
Data Alignment..................................................................................................... 289
Common Control Register (CMNCR) .................................................................. 291
CSn Space Bus Control Register (CSnBCR) ........................................................ 294
CSn Space Wait Control Register (CSnWCR) ..................................................... 299
SDRAM Control Register (SDCR)....................................................................... 325
Rev. 3.00 Jan. 18, 2008 Page xv of lxii