HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 286

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Exception Handling
unconditional delayed branch instruction or an instruction following a conditional delayed branch
instruction whose branch condition is satisfied. If a branch does not occur in a conditional delayed
branch, the normal processing is executed.
(3)
Acceptance priorities are determined for all exception requests. The priority of resets, general
exceptions, and interrupts are determined in this order: a reset is always accepted regardless of the
CPU status. Interrupts are accepted only when resets or general exceptions are not requested.
If multiple general exceptions occur simultaneously in the same instruction, the priority is
determined as follows.
1. A processing-completion type exception generated at the previous instruction*
2. A user break before instruction execution (re-execution type)
3. An exception related to an instruction fetch (CPU address error and MMU related exceptions:
4. An exception caused by an instruction decode (General illegal instruction exceptions and slot
5. An exception related to data access (CPU address error and MMU related exceptions: re-
6. Unconditional trap (processing-completion type)
7. A user break other than one before instruction execution (processing-completion type)
8. DMA address error (processing-completion type)
Note: * If a processing-completion type exception is accepted at an instruction, exception
Only one exception is accepted at a time. Accepting multiple exceptions sequentially results in all
exception requests being processed.
Rev. 3.00 Jan. 18, 2008 Page 224 of 1458
REJ09B0033-0300
re-execution type)
illegal instruction exceptions: re-execution type, unconditional trap: processing-completion
type)
execution type)
Acceptance Priority and Test Priority
processing starts before the next instruction is executed. This exception processing
executed before an exception generated at the next instruction is detected.