HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 405

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.5.3
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in
read access and in write access. The areas other than 4, 5A, and 5B have common access wait for
read cycle and write cycle. The specified number of Tw cycles is inserted as wait cycles in a
normal space access shown in figure 9.9.
When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 9.10. A 2-cycle wait is specified as a software
wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw
cycle to the T2 cycle.
Access Wait Control
Figure 9.9
Read
Write
Wait Timing for Normal Space Access (Software Wait Only)
Note: * The waveform for DACKn is when active low is specified.
A25 to A0
D31 to D0
D31 to D0
DACKn*
WEn (BEn)
RD/WR
CKIO
CSn
RD
BS
T1
Tw
Rev. 3.00 Jan. 18, 2008 Page 343 of 1458
Section 9
T2
Bus State Controller (BSC)
REJ09B0033-0300