HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 170

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 3 DSP Operating Unit
In single data transfer instructions, all bits in 32-bit address are valid.
3.4.3
In double data transfer instructions, a module addressing can be used. If the address pointer value
reaches the preset modulo end address while a modulo addressing mode is specified,, the address
pointer value becomes the modulo start address.
To control modulo addressing, the modulo register (MOD) extended in the DSP mode and the
DMX and DMY bits of the SR register are used.
The MOD register is provided to set the start and end addresses of the modulo address area. The
upper and lower words of the MOD register store modulo start address (MS) and modulo end
address (ME), respectively. The LDC and STC instructions are extended for MOD register
handling.
If the DMX bit in the SR register is set, the modulo addressing is specified for the X address
register. If the DMY bit in the SR register is set, the modulo addressing is specified for the Y
address register. Modulo addressing is valid for either the X or the Y address register, only; it
cannot be set for both at the same time. Therefore, DMX and DMY cannot both be set
simultaneously (if they are, the DMY setting will be valid). ( In the future, this specification may
be changed.) The MDX and MDY bits of the SR can be specified by the STC or LDC instruction
for the SR register.
If an exception is accepted during modulo addressing, the MDX and MDY bits of the SR and
MOD register must be saved. By restoring these register values, a control is returned to the
modulo addressing after an exception handling.
Table 3.11 Modulo Addressing Control Instructions
Rev. 3.00 Jan. 18, 2008 Page 108 of 1458
REJ09B0033-0300
Instruction
STC MOD,Rn
STC.L MOD,Rn
LDC.L @Rn+,MOD
LDC Rn,MOD
Modulo Addressing
Operation
MOD → Rn
Rn – 4 → Rn, MOD → (Rn)
(Rn) → Rn, Rn + 4 → Rn
Rn → MOD
Execution States
1
1
4
4