HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 929

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

26.3.1
This LCDC can select the bus clock (Bφ), the peripheral clock (Pφ), or the external clock
(LCD_CLK) as its operation clock source. The selected clock source can be divided using an
internal divider into a clock of 1/1 to 1/32 and be used as the LCDC operating clock (DOTCLK).
The clock output from the LCDC is used to generate the synchronous clock output (LCD_CL2)
for the LCD panel from the operating clock selected in this register. For a TFT panel, LCD_CL2 =
DOTCLK, and for an STN or DSTN panel, LCD_CL2 = a clock with a frequency of
(DOTCLK/data bus width of output to LCD panel). The LDICKR must be set so that the clock
input to the LCDC is 66 MHz or less regardless of the LCD_CL2.
Bit
15, 14
13
12
11 to 9
8
7, 6
5
4
3
2
1
0
LCDC Input Clock Register (LDICKR)
Bit Name

ICKSEL1
ICKSEL0



DCDR5
DCDR4
DCDR3
DCDR2
DCDR1
DCDR0
Initial Value
All 0
0
0
All 0
1
All 0
0
0
0
0
0
1
R/W
R
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Input Clock Select
Set the clock source for DOTCLK.
00: Bus clock is selected (Bφ)
01: Peripheral clock is selected (Pφ)
10: External clock is selected (LCD_CLK)
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
This bit is always read as 1. The write value
should always be 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Division Ratio
Set the input clock division ratio. For details on the
setting, refer to table 26.2.
Rev. 3.00 Jan. 18, 2008 Page 867 of 1458
Section 26
LCD Controller (LCDC)
REJ09B0033-0300