HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 72

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 1
1.2
1.3
1.3.1
Rev. 3.00
REJ09B0033-0300
External bus
CPU/DSP (16 kbytes)
interface (H-UDI)
CPU core
User debugging
Super H
Serial communication
interface 0 with FIFO
Instruction/data for
X/Y memory
128-byte FIFO
(SCIF0/IrDA)
interface
SD host
(SDHI)
Bus state
controller
Block Diagram
DSP core
(BSC)
Pin Assignments
Pin Assignments
Jan. 18, 2008
Overview
controller
Interrupt
Peripheral bus
(INTC)
Internal bus
128-byte FIFO (SCIF1)
Serial communication
interface 1 with FIFO
controller (UBC)
controller (CCN)
X bus
Y bus
Cache access
User break
Realtime
bus controller
(RTC)
Peripheral
clock
Page 10 of 1458
Clock pulse
(32 kbytes)
generator
memory
(CPG)
Cache
access controller
Direct memory
I
2
C
(DMAC)
Figure 1.1
576-byte
128-byte
SRAM
RAM
Timer unit
management
(TMU)
unit (MMU)
CPU bus
Memory
interface (MMCIF)
MultiMediaCard
interface (AFEIF)
Analog front end
accelerator
(SSL)
SSL
Block Diagram
Peripheral bus
Internal bus
256-byte
SRAM
USB host
controller
USB function controller
(USBH)
1-kbyte FIFO (USBF)
with FIFO
Serial I/O
(SIOF0)
512-byte
RAM
256-byte
timer (CMT)
SRAM
controller
Compare
(LCDC)
match
LDC
with FIFO
Serial I/O
(SIOF1)
2.56-kbyte
timer pulse
line buffer
unit (TPU)
16-bit
SIM card
interface
converter
(SIM)
(ADC)
A/D
converter
controller
(DAC)
PC card
(PCC)
D/A

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