HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 837

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
4
3
2
1
0
Bit Name
UE
RD
SF
WDH
SO
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Unrecoverable Error
This bit is set when the host controller detects a system
error that is not related to USB. HCD clears this bit after
the host controller is reset.
0: System error is not generated
1: System error is detected
Resume Detected
This bit is set when the host controller detects that a
device of USB issues a resume signal. This bit is not set
when HCD sets USB Resume state.
0: The resume signal is not detected
1: The resume signal is detected
Start of Frame
This bit is set by the host controller when each frame
starts and after the Hcca Frame Number is updated. The
host controller simultaneously generates the SOF token.
0: Each frame has not initiated or Hcca Frame Number is
1: Initiation of each frame and updating of Hcca Frame
Write-back Done Head
This bit is set immediately after the host controller has
written Hc Done Head to Hcca Done Head. Hcca Done
Head is not updated until this bit is cleared. HCD should
clear this bit only after the content of Hcca Done Head has
been stored.
0: When cleared after set to 1
1: When Hc Done Head is written to Hcca Done head
Scheduling Overrun
This bit is set when the USB schedule has overrun after
Hcca Frame Number has updated. SchedulingOverrun
also increments the SOC bit in USBHCS.
0: The USB schedule has not overrun
1: The USB schedule has overrun
not updated
Number
Rev. 3.00 Jan. 18, 2008 Page 775 of 1458
Section 24
USB Host Controller (USBH)
REJ09B0033-0300