HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1191

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

4. When an instruction fetch cycle is set for channel B, the break data register B (BDRB) is
5. If the I bus is set for a break of an instruction fetch cycle, the condition is determined for the
33.3.3
1. If the L bus is specified as a break condition for data access break, condition comparison is
2. The relationship between the data access cycle address and the comparison condition for each
Table 33.3 Data Access Cycle Addresses and Operand Size Comparison Conditions
Access Size
Longword
Word
Byte
ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle.
instruction fetch cycles on the I bus. For details, see No.5 in section 33.3.1, Flow of the User
Break Operation.
performed for the virtual addresses (and data) accessed by the executed instructions, and a
break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition
comparison is performed for the physical addresses (and data) of the data access cycles that are
issued on the I bus by all bus masters including the CPU, and a break occurs if the condition is
satisfied. For details on the CPU bus cycles issued on the I bus, see No.5 in section 33.3.1,
Flow of the User Break Operation.
operand size is listed in table 33.3.
This means that when address H'00001003 is set in the break address register (BARA or
BARB), for example, the bus cycle in which the break condition is satisfied is as follows
(where other conditions are met).
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
Break on Data Access Cycle
Compares break address register bits 31 to 0 to address bus bits 31 to 0
Address Compared
Compares break address register bits 31 to 2 to address bus bits 31 to 2
Compares break address register bits 31 to 1 to address bus bits 31 to 1
Rev. 3.00 Jan. 18, 2008 Page 1129 of 1458
Section 33 User Break Controller (UBC)
REJ09B0033-0300