HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 686

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 18
Figure 18.10 shows an example of the operation when modem control is used.
Transmit data
TxD
When modem control is enabled, the RTS signal goes high after the number of receive FIFO
(SCFRDR) has exceeded the number of RTS output triggers.
18.4.3
Operation in synchronous mode is described below.
The SCIF has 64-stage FIFO buffers for both transmission and reception, reducing the CPU
overhead and enabling fast, continuous communication to be performed.
The operating clock source is selected using the serial mode register (SCSMR). The SCIF clock
source is determined by the CKE1 and CKE0 bits in the serial control register (SCSCR).
• Transmit/receive format: Fixed 8-bit data
• Indication of the number of data bytes stored in the transmit and receive FIFO registers
• Internal clock or external clock used as the SCIF clock source
Rev. 3.00 Jan. 18, 2008 Page 624 of 1458
REJ09B0033-0300
CTS
When the internal clock is selected:
The SCIF operates on the baud rate generator clock and outputs a serial clock from SCK pin.
Transmit data
TxD
RTS
Synchronous Mode
Serial Communication Interface with FIFO (SCIF)
Start
bit
0
Start
bit
D0
0
Figure 18.10
Figure 18.11
Transmission stops
when CTS goes high
D1
D0
RTS goes high when receive data is
at least number of RTS output trigger
D1
D6
Example of RTS Control Operation
D7
Example of CTS Control Operation
D6
Parity
bit
0/1
D7
Stop
bit
Parity
bit
0/1
Stop
bit
RTS goes low when receive data is
less than number of RTS output trigger
Transmission starts again
when CTS goes low
Start
bit
0
D0
D1
D6
D7
0/1