HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 684

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 18
In serial reception, the SCIF operates as described below.
1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
Rev. 3.00 Jan. 18, 2008 Page 622 of 1458
REJ09B0033-0300
synchronization and starts reception.
After receiving these bits, the SCIF carries out the following checks.
A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
B. The SCIF checks whether receive data can be transferred from the receive shift register
C. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not
the first is checked.
(SCRSR) to SCFRDR.
set.
Serial Communication Interface with FIFO (SCIF)
No
No
No
Read receive data in SCFRDR
Clear DR, ER, BRK flags in
Receive error processing
Figure 18.8
Break processing
Error processing
SCSSR to 0
BRK= 1?
ER = 1?
DR= 1?
End
Yes
Yes
Sample Serial Reception Flowchart (2)
1. Whether a framing error or parity error has
2. When a break signal is received, receive data
occurred in the receive data read from
SCFRDR can be ascertained from the FER and
PER bits in SCSSR.
is not transferred to SCFRDR while the BRK
flag is set. However, note that the last data in
SCFRDR is H'00 and the break data in which a
framing error occurred is stored.