HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 667
HD6417320
Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417320.pdf
(1524 pages)
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Bit
1
Bit Name Initial Value R/W
RDF
0
R/(W)*
Section 18
Description
Receive FIFO Data Full
Indicates that received data is transferred to the
receive FIFO data register (SCFRDR), the number of
data in SCFRDR becomes more than the number of
receive triggers specified by the RTRG1 and RTRG0
bits in SCFCR.
0: The number of transmit data written to SCFRDR is
[Clearing conditions]
•
•
1: The number of receive data in SCFRDR is more
[Setting condition]
The number of receive data which is greater than the
specified number of receive triggers is being stored to
SCFRDR.*
Note:
less than the specified number of receive triggers
than the specified number of receive triggers
Power-on reset, manual reset
SCFRDR is read until the number of receive data
in SCFRDR becomes less than the specified
number of receive triggers, and RDF is read as 1,
then written to with 0.
*
Serial Communication Interface with FIFO (SCIF)
Since SCFTDR is a 64-byte FIFO
register, the maximum number of data
which can be read when RDF is 1 is the
specified number of receive triggers. If
attempted to read after all data in
SCFRDR have been read, the data is
undefined. The number of receive data in
SCFRDR is indicated by the lower bits of
SCFTDR.
Rev. 3.00 Jan. 18, 2008 Page 605 of 1458
REJ09B0033-0300
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