HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 480

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10
10.3.5
DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the
DMA transfer. This register shows the DMA transfer status.
Rev. 3.00 Jan. 18, 2008 Page 418 of 1458
REJ09B0033-0300
Bit
15, 14
13
12
11, 10
9
8
7 to 3
Bit Name

CMS1
CMS0

PR1
PR0

DMA Operation Register (DMAOR)
Direct Memory Access Controller (DMAC)
Initial
Value
All 0
0
0
All 0
0
0
All 0
R/W
R
R/W
R/W
R
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Cycle Steal Mode Select 1, 0
Select either normal mode or intermittent mode in cycle
steal mode.
It is necessary that all channel's bus modes are set to
cycle steal mode to make valid intermittent mode.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
11: Intermittent mode 64
Reserved
These bits are always read as 0. The write value should
always be 0.
Priority Mode 1, 0
Select the priority level between channels when there are
transfer requests for multiple channels simultaneously.
00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5
01: CH0 > CH2 > CH3 > CH1 > CH4 > CH5
10: Setting prohibited
11: Round-robin mode
Reserved
These bits are always read as 0. The write value should
always be 0.
Executes one DMA transfer in each of 16 clocks of an
external bus clock.
Executes one DMA transfer in each of 64 clocks of an
external bus clock.