HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 469

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

This LSI includes the direct memory access controller (DMAC).
The DMAC can be used in place of the CPU to perform high-speed transfers between external
devices that have DACK (transfer request acknowledge signal), external memory, on-chip
memory, memory-mapped external devices, and on-chip peripheral modules.
10.1
• Six channels (two channels can receive an external request)
• 4-Gbyte physical address space
• Data transfer unit is selectable: Byte, word (2 bytes), longword (4 bytes), and 16 bytes
• Maximum transfer count: 16,777,216 transfers
• Address mode: Dual address mode or single address mode can be selected.
• Transfer requests:
• Selectable bus modes:
• Selectable channel priority levels:
• Interrupt request: An interrupt request can be generated to the CPU after transfers end by the
• External request detection: There are following four types of DREQ input detection.
• Transfer request acknowledge signal:
DMAS301A_010020030200
Section 10
(longword × 4)
External request, on-chip peripheral module request, or auto request can be selected.
The following modules can issue an on-chip peripheral module request.
 SCIF0, SIOF1, MMC, CMT (channels 0 to 4), SIM, USBF, SIOF0, SIOF1, ADC, and
Cycle steal mode (normal mode and intermittent mode) or burst mode can be selected.
The channel priority levels are selectable between fixed mode and round-robin mode.
specified counts.
 Low level detection
 High level detection
 Rising edge detection
 Falling edge detection
Active levels for DACK and TEND can be set independently.
SDHI
Features
Direct Memory Access Controller (DMAC)
Section 10
Rev. 3.00 Jan. 18, 2008 Page 407 of 1458
Direct Memory Access Controller (DMAC)
REJ09B0033-0300