HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 112

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2
Note: The M, Q, S, and T bits can be set/cleared by the user mode specific instructions. Other bits
(2)
The save status register (SSR) can be accessed only in privileged mode. Before entering the
exception, the contents of the SR register is stored in the SSR register. At reset, the SSR initial
value is undefined.
(3)
The save program counter (SPC) can be accessed only in privileged mode. Before entering the
exception, the contents of the PC is stored in the SPC. At reset, the SPC initial value is undefined.
(4)
The global base register (GBR) is referenced as a base register in GBR indirect addressing mode.
At reset, the GBR initial value is undefined.
(5)
The vector base register (VBR) can be accessed only in privileged mode. If a transition from reset
state to exception handling state occurs, this register is referenced as a base address. For details,
refer to section 7, Exception Handling. At reset, the VBR is initialized as H'00000000.
Rev. 3.00 Jan. 18, 2008 Page 50 of 1458
REJ09B0033-0300
Bit
0
Save Status Register (SSR)
Save Program Counter (SPC)
Global Base Register (GBR)
Vector Base Register (VBR)
can be read or written in privileged mode.
CPU
Bit Name
T
Initial
Value

R/W
R/W
Description
T Bit
Indicates true or false for compare instructions or carry
or borrow occurrence for an operation instruction with
carry or borrow. This bit can be specified by the SETT
and CLRT instructions in user mode.
At reset, this bit is undefined. This bit is not affected in
an exception handling state.