HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 861

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

24.4.2
ED (endpoint descriptor) and TD (transfer descriptor) that define each transfer transaction of USB
Host Controller must be aligned so that each Dword corresponds to the long-word boundary
(addresses 4n to 4n + 3) of the memory.
24.5
24.5.1
The transferred data is stored in shared system memory with CPU. The data alignment in system
memory are restricted depends on SDRAM specification which is used as system memory.
In above figure, transfer data 1 and 3 are able to be read or written by USB Host Controller. But
transfer data 2 are possibly unable to be read or written by USB Host controller. Any data, which
have possibility to be accessed by USB Host Controller, must be aligned in SDRAM not to cross
row address alignment.
Storage Format of the Descriptor
Data Alignment Restriction of USB Host Controller
Restriction on the Line Boundary of the Synchronous DRAM
DRAM
Row address
Row address
Row address
n
n+1
n+2
Memory area
(2)
Rev. 3.00 Jan. 18, 2008 Page 799 of 1458
Section 24
(3)
USB Host Controller (USBH)
(1)
REJ09B0033-0300