HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 430

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9
When bank active mode is set, if only accesses to the respective banks in the area 3 space are
considered, as long as accesses to the same row address continue, the operation starts with the
cycle in figure 9.19 or 9.22, followed by repetition of the cycle in figure 9.20 or 9.23. An access to
a different area during this time has no effect. If there is an access to a different row address in the
bank active state, after this is detected the bus cycle in figure 9.21 or 9.24 is executed instead of
that in figure 9.20 or 9.23. In bank active mode, too, all banks become inactive after a refresh
cycle or after the bus is released as the result of bus arbitration.
Rev. 3.00 Jan. 18, 2008 Page 368 of 1458
REJ09B0033-0300
Bus State Controller (BSC)
A12/A11*
D31 to D0
A25 to A0
DACKn*
RD/WR
DQMxx
CKIO
RAS
CAS
CSn
BS
Figure 9.19
1
2
Notes:
1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Tr
Burst Read Timing (No Auto-Precharge)
Tc1
Td1
Tc2
Td2
Tc3
Tc4
Td3
Td4
Tde