HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1469

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
Section 10 Direct Memory Access
Controller (DMAC)
10.2 Input/Output Pins
Table 10.1 Pin Configuration
Section 10 Direct Memory Access
Controller (DMAC)
10.4.2 DMA Transfer Requests
(3)
Table 10.18 Example of BSC
Ordinary Memory Access (No
Wait, Idle Cycle 1, Longword
Access to 16-Bit Device)
10.5 Usage Notes
10.5.2 Notes on the Cases When
DACK is Divided
Page Revision (See Manual for Details)
409
428
447
448
Section 10.5.2 added
Amended
Changed
Added
….Transfer request signals comprise the transmit data
empty transfer request and receive data full transfer
request from the ADC set by CHCR0 to CHCR5 and
the SCIF0, SCIF1, MMC, USBF, SIM, SIOF0, SIOF1,
and SDHI set by DMARS0/1/2,…. These conditions
also apply to the SIOF1, MMC, USBF, SIM, SIOF0,
SIOF1, and SDHI…..
Channel Name
0
1
DMA transfer request DREQ0
DMA transfer request
reception
DMA transfer end
DMA transfer request DREQ1
DMA transfer request
reception
DMA transfer end
(Active-low)
Note: The DACK is asserted for the last transfer unit
Address
DACKn
Rev. 3.00 Jan. 18, 2008 Page 1407 of 1458
CKIO
WAIT
WEn
of the DMA transfer. When the transfer unit is
divided into several bus cycles and the CSn is
negated between bus cycles, the DACK is also
divided.
Data
CSn
RD
T1
T2
Taw
T1
Pin
Name
DACK0
TEND0
DACK1
TEND1
T2
REJ09B0033-0300
I/O
Input
Output
Output
Input
Output
Output