HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 904

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25
• Data Stage (Control-Out)
The application first analyzes command data from the host in the setup stage, and determines the
subsequent data stage direction. If the result of command data analysis is that the data stage is out-
transfer, the application waits for data from the host, and after data is received (IFR0/EP0o TS =
1), reads data from the FIFO. Next, the application writes 1 to the EP0o read complete bit, empties
the receive FIFO, and waits for reception of the next data.
The end of the data stage is identified when the host transmits an IN token and the status stage is
entered.
Rev. 3.00 Jan. 18, 2008 Page 842 of 1458
REJ09B0033-0300
USB Function Controller (USBF)
Data reception from host
OUT token reception
OUT token reception
(IFR0/EP0o TS = 1)
Set EP0o reception
USB function
complete flag
to TRG/EP0o
Figure 25.8
to TRG/EP0s
1 written
1 written
RDFN?
RDFN?
Yes
Yes
ACK
Data Stage (Control-Out) Operation
No
No
NAK
NAK
Interrupt request
receive data size register
data register (EPDR0o)
(TRG/EP0o RDFN = 1)
Read data from EP0o
Read data from EP0o
Clear EP0o reception
Write 1 to EP0o read
(IFR0/EP0o TS = 0)
complete flag
Application
complete bit
(EPSZ0o)