HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 181

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 3.18 Correspondence between DSP Instruction Operands and Registers
When writing parallel instructions, the field-B instruction is written first, followed by the field-A
instruction. A sample parallel processing program is shown in figure 3.6.
Square brackets mean that the contents can be omitted.
The no operation instructions NOPX and NOPY can be omitted. For details on the field B in DSP
data operation instructions, refer to section 3.6.4, DSP Operation Instructions.
The DSR register condition code bit (DC) is always updated on the basis of the result of an
unconditional ALU or shift operation instruction. Conditional instructions do not update the DC
bit. Multiply instructions, also, do not update the DC bit. DC bit updating is performed by means
of the CS[2:0] bits in the DSR register. The DC bit update rules are shown in table 3.19.
Register
A0
A1
M0
M1
X0
X1
Y0
Y1
DCF
PADD
PINC
PCMP
Sx
Yes
Yes
Yes
Yes
A0,
M1,
M1,
Figure 3.6 Sample Parallel Instruction Program
M0,
A1
M0
Sy
Yes
Yes
Yes
Yes
A0
ALU Operations
PMULS X0, Y0, M0
Dz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Du
Yes
Yes
Yes
Yes
MOVX.W
MOVX.W
MOVX.W
Rev. 3.00 Jan. 18, 2008 Page 119 of 1458
@R4+,
@R5+R8,
@R4,
Se
Yes
Yes
Yes
Yes
X0
X0
X1
Multiply Operations
Section 3 DSP Operating Unit
Sf
Yes
Yes
Yes
Yes
MOVY.W
MOVY.W
[NOPY]
REJ09B0033-0300
@R6+,
@R7+,
Dg
Yes
Yes
Yes
Yes
Y0
Y1