HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 13

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

4.4
4.5
4.6
4.7
Section 5 Cache ...................................................................................................197
5.1
5.2
5.3
5.4
4.3.2
4.3.3
4.3.4
MMU Functions................................................................................................................. 183
4.4.1
4.4.2
4.4.3
4.4.4
MMU Exceptions............................................................................................................... 188
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
Memory-Mapped TLB....................................................................................................... 194
4.6.1
4.6.2
4.6.3
Usage Note......................................................................................................................... 196
Features.............................................................................................................................. 197
5.1.1
Register Descriptions ......................................................................................................... 199
5.2.1
5.2.2
5.2.3
Operation ........................................................................................................................... 205
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
Memory-Mapped Cache .................................................................................................... 209
5.4.1
5.4.2
5.4.3
TLB Indexing........................................................................................................ 179
TLB Address Comparison .................................................................................... 180
Page Management Information............................................................................. 182
MMU Hardware Management .............................................................................. 183
MMU Software Management ............................................................................... 184
MMU Instruction (LDTLB).................................................................................. 184
Avoiding Synonym Problems ............................................................................... 186
TLB Miss Exception............................................................................................. 188
TLB Protection Violation Exception .................................................................... 189
TLB Invalid Exception ......................................................................................... 190
Initial Page Write Exception................................................................................. 191
MMU Exception in Repeat Loop.......................................................................... 192
Address Array ....................................................................................................... 194
Data Array ............................................................................................................ 194
Usage Examples.................................................................................................... 196
Cache Structure..................................................................................................... 197
Cache Control Register 1 (CCR1) ........................................................................ 200
Cache Control Register 2 (CCR2) ........................................................................ 201
Cache Control Register 3 (CCR3) ........................................................................ 204
Searching the Cache.............................................................................................. 205
Read Access.......................................................................................................... 207
Prefetch Operation ................................................................................................ 207
Write Access ......................................................................................................... 207
Write-Back Buffer ................................................................................................ 208
Coherency of Cache and External Memory .......................................................... 208
Address Array ....................................................................................................... 209
Data Array ............................................................................................................ 210
Usage Examples.................................................................................................... 212
Rev. 3.00 Jan. 18, 2008 Page xiii of lxii