HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 693
HD6417320
Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417320.pdf
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Figure 18.15 shows sample flowcharts for serial reception.
Data Transfer Operations (Serial Data Reception)
When using receive FIFO data interrupt,
Read receive trigger number of receive
Set receive trigger number in RTRG1
Figure 18.15
Clear RE bit in SCSCR to 0
data bytes from SCFRDR
and RTRG0 in SCFCR
Set RE bit in SCSCR
Start of reception
End of reception
set RIE bit to 1
RDF =1?
(First Reception after Initialization)
Yes
Sample Serial Reception Flowchart (1)
Section 18
No
1
2
3
4
1. Set the receive trigger number
2. Reception is started when the
3. Read receive data while the
4. After the end of reception, clear
Serial Communication Interface with FIFO (SCIF)
in SCFCR.
RE bit in SCSCR is set to 1.
RDF bit is 1.
the RE bit to 0.
Rev. 3.00 Jan. 18, 2008 Page 631 of 1458
REJ09B0033-0300
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