HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 64

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 1
Table 1.1
Rev. 3.00
REJ09B0033-0300
Item
CPU
DSP operating
unit
Jan. 18, 2008
Overview
SH7720/SH7721 Features
Features
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Renesas Technology Original SuperH architecture
Upper compatibility with SH-1, SH-2, and SH3-DSP at object code level
32-bit internal data bus
General-register
 Sixteen 32-bit general registers (eight 32-bit shadow registers)
 Five 32-bit control registers
 Four 32-bit system registers
RISC type instruction set
 Instruction length: 16-bit fixed length for improved code efficiency
 Load/store architecture
 Delayed branch instruction
 Instruction set based on C language
Instruction execution time: One instruction/cycle for basic instructions
Logical address space: 4 Gbytes
Space identifier ASID: 8 bits, 256 logical address spaces
Five-stage pipeline
Mixture of 16-bit and 32-bit instructions
32-/40-bit internal data bus
Multiplier, ALU, barrel shifter, and DSP register
16-bit x 16-bit → 32-bit one cycle multiplier
Large-capacity DSP data register file
 Six 32-bit data registers
 Two 40-bit data registers
Extended Harvard architecture for DSP data buses
 Two data buses
 One instruction bus
Up to four parallel operations: ALU, multiply, two loads, and store
Two address units to generating addresses for two memory access
DSP data addressing modes: Increment, index register addition (with or
without modulo addressing)
Zero-overhead repeat loop control
Conditional execution instructions
User DSP mode and privileged DSP mode
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