HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 132

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2
Note:
Rev. 3.00 Jan. 18, 2008 Page 70 of 1458
REJ09B0033-0300
Instruction
EXTS.B
EXTS.W
EXTU.B
EXTU.W
MAC.L
MAC.W
MUL.L
MULS.W
MULU.W
NEG
NEGC
SUB
SUBC
SUBV
*
CPU
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
@Rm+,
@Rn+
@Rm+,
@Rn+
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
The number of execution cycles indicated within the parentheses ( ) are required when
the operation result is read from the MACH/MACL register immediately after the
instruction.
Instruction Code Operation
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm1111
0100nnnnmmmm1111
0000nnnnmmmm0111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
0011nnnnmmmm1010
0011nnnnmmmm1011
A byte in Rm is sign-extended
→ Rn
A word in Rm is sign-extended
→ Rn
A byte in Rm is zero-extended
→ Rn
A word in Rm is zero-
extended → Rn
Signed operation of (Rn) ×
(Rm) + MAC → MAC,
Rn + 4 → Rn, Rm + 4 → Rm
32 × 32 + 64 → 64 bits
Signed operation of (Rn) ×
(Rm) + MAC → MAC,
Rn + 2 → Rn, Rm + 2 → Rm
16 × 16 + 64 → 64 bits
Rn × Rm → MACL
32 × 32 → 32 bits
Signed operation of Rn × Rm
→ MACL
16 × 16 → 32 bits
Unsigned operation of
Rn × Rm → MACL
16 × 16 → 32 bits
0–Rm→Rn
0–Rm–T→Rn, Borrow→T
Rn–Rm→Rn
Rn–Rm–T→Rn, Borrow →T
Rn–Rm→Rn, Underflow→T
Privileged
Mode
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Cycles
1
1
1
1
2 (to 5)* –
2 (to 5)* –
2 (to 5) * –
1( to 3)* –
1(to 3)*
1
1
1
1
1
T Bit
–
–
–
–
–
–
Borrow
–
Borrow
Underflow