HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 953

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

26.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR)
LDPSPR controls the power supply circuit that provides power to the LCD module. The timing to
start outputting the timing signals to the LCD_VEPWC and LCD_VCPWC pins is specified.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
Bit Name
ONA3
ONA2
ONA1
ONA0
ONB3
ONB2
ONB1
ONB0
OFFE3
OFFE2
OFFE1
OFFE0
1
1
1
1
0
1
1
0
0
0
0
0
Initial Value R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
LCDC Power-On Sequence Period
Set the period from LCD_VCPWC assertion to
starting output of the display data (LCD_DATA) and
timing signals (LCD_FLM, LCD_CL1, LCD_CL2,
and LCD_M_DISP) in the power-on sequence of
the LCD module in frame units.
Specify to the value of (the period)-1.
This period is the (a) period in figures 26.4 to 26.7,
Power-Supply Control Sequence and States of the
LCD Module.
LCDC Power-On Sequence Period
Set the period from starting output of the display
data (LCD_DATA) and timing signals (LCD_FLM,
LCD_CL1, LCD_CL2, and LCD_M_DISP) to the
LCD_VEPWC assertion in the power-on sequence
of the LCD module in frame units.
Specify to the value of (the period)-1.
This period is the (b) period in figures 26.4 to 26.7,
Power-Supply Control Sequence and States of the
LCD Module.
LCDC Power-Off Sequence Period
Set the period from LCD_VEPWC negation to
stopping output of the display data (LCD_DATA)
and timing signals (LCD_FLM, LCD_CL1,
LCD_CL2, and LCD_M_DISP) in the power-off
sequence of the LCD module in frame units.
Specify to the value of (the period)-1.
This period is the (e) period in figures 26.4 to 26.7,
Power-Supply Control Sequence and States of the
LCD Module.
Rev. 3.00 Jan. 18, 2008 Page 891 of 1458
Section 26
LCD Controller (LCDC)
REJ09B0033-0300