HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 781

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

21.4.6
(1)
The transmit and receive FIFOs of the SIOF have the following features.
• 16-stage 32-bit FIFOs for transmission and reception
• The FIFO pointer can be updated in one read or write cycle regardless of access size of the
(2)
The transfer request of the FIFO can be issued to the CPU or DMAC as the following interrupt
sources.
• FIFO transmit request: TDREQ (transmit interrupt source)
• FIFO receive request: RDREQ (receive interrupt source)
The request conditions for FIFO transmit or receive can be specified individually. The request
conditions for the FIFO transmit and receive are specified by the TFWM2 to TFWM0 bits and
RFWM2 to RFWM0 bits in SIFCTR, respectively. Tables 21.9 and 21.10 summarize the
conditions specified by SIFCTR.
Table 21.9 Conditions to Issue Transmit Request
TFWM2 to TFWM0
000
100
101
110
111
CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.)
Overview
Transfer Request
FIFO
Number of
Requested Stages
1
4
8
12
16
Transmit Request
Empty area is 16 stages
Empty area is 12 stages or more
Empty area is 8 stages or more
Empty area is 4 stages or more
Empty area is 1 stage or more
Rev. 3.00 Jan. 18, 2008 Page 719 of 1458
Section 21
Serial I/O with FIFO (SIOF)
REJ09B0033-0300
Used Areas
Smallest
Largest