HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 688

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 18
(3)
Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0,
then initialize the SCIF as described below.
When the clock source, etc., is changed, the TE and RE bits must be cleared to 0 before making
the change using the following procedure. When the TE bit is cleared to 0, the transmit shift
register (SCTSR) is initialized. Note that clearing the TE and RE bits to 0 does not change the
contents of SCSSR, SCFTDR, or SCFRDR. The TE bit should be cleared to 0 after all transmit
data has been sent and the TEND bit in SCSSR has been set to 1. The TE bit should not be cleared
to 0 during transmission; if attempted, the TxD pin will go to the high-impedance state. Before
setting TE to 1 again to start transmission, the TFRST bit in SCFCR should first be set to 1 to reset
SCFTDR.
Figure 18.13 shows sample SCIF initialization flowcharts.
Rev. 3.00 Jan. 18, 2008 Page 626 of 1458
REJ09B0033-0300
Data Transfer Operations (SCIF Initialization)
Figure 18.13
Serial Communication Interface with FIFO (SCIF)
number, and clear TDFE flag to 0 after
data exceeding transmit trigger setting
Set transmit trigger number in TTRG1
and TTRG0 in SCFCR, write transmit
(leaving TE and RE bits cleared to 0)
Clear TE and RE bits in SCSCR to 0
Set CKE1 and CKE0 bits in SCSCR
Set TFRST bit in SCFCR to 1
Set C/A bit in SCSMR to 1
Set CKS1 and CKS0 bits
1-bit interval elapsed?
Clear TFRST bit to 0
Set value in SCBRR
reading 1 from it
Sample SCIF Initialization Flowchart (1) (Transmission)
Initialization
End
Yes
Wait
No
1
2
3
4
5
6
7
1. Be sure to set the TFRST bit in
2. Set the clock selection in SCSCR.
3. Set the clock source selection in
4. Write a value corresponding to the
5. Clear the TFRST bit in SCFCR to 0.
6. Set the transmit trigger number,
7. Wait one bit interval.
SCFCR to 1, to reset the FIFOs.
Be sure to clear bits RIE, TIE, TE,
and RE to 0.
SCSMR.
bit rate into SCBRR.
write transmit data exceeding the
transmit trigger setting number, and
clear the TDFE flag to 0 after reading
it.