HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 157
HD6417320
Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417320.pdf
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• Example 6: Repeat loop consisting of three instructions (extended to the instruction stream
• Example 7: Repeat loop consisting of two instructions (extended to the instruction stream
• Example 8: Repeat loop consisting of one instruction instructions (extended to the instruction
In the DSP mode, the system control instructions (LDC and STC) that handle the RS and RE
registers are extended. The RC[11:0] bits and RF[1:0] bits of the SR can be controlled by the LDC
and STC instructions for the SR register. These instructions should be used if an exception is
enabled during repeat loop execution. The repeat loop can be resumed correctly by storing the RS
and RE register values and RC[11:0] bits and RF[1:0] bits of the SR register before exception
handling and by restoring the stored values after exception handling. However, note that there are
some restrictions on exception acceptance during repeat loop execution. For details refer to
Restrictions on Repeat Loop Control in section 3.3.1, DSP Repeat Control and section 7,
Exception Handling.
RptStart: instr1
RptEnd:
RptStart: instr1
RptEnd:
RptStart:
RptEnd:
shown in example 2, above)
shown in example 3, above)
stream shown in example 4, above)
REPEAT RptStart, RptEnd, #4
instr0
instr2
instr3
REPEAT RptStart, RptEnd, #4
instr0
instr2
REPEAT RptStart, RptEnd, #4
instr0
instr1
;
; [Repeat start instruction]
;
; [Repeat end instruction]
;
; [Repeat start instruction]
; [Repeat end instruction]
;
; [Repeat start instruction]==[Repeat end
instruction]
Rev. 3.00 Jan. 18, 2008 Page 95 of 1458
Section 3 DSP Operating Unit
REJ09B0033-0300
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