HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 289

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.3
This section describes the conditions for specific exception handling, and the processor operations.
This section describes resets and general exceptions. For interrupt operations, refer to section 8,
Interrupt Controller (INTC).
7.3.1
(1)
• Conditions
• Operations
(2)
• Conditions
• Operations
7.3.2
(1)
• Conditions
• Types
Power-on reset is request
Set EXPEVT to H'000, initialize the CPU and on-chip peripheral modules, and branch to the
reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections.
Manual reset is request
Set EXPEVT to H'020, initialize the CPU and on-chip peripheral modules, and branch to the
reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections.
 Instruction is fetched from odd address (4n + 1, 4n + 3)
 Word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3)
 Longword is accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
 The area ranging from H'80000000 to H'FFFFFFFF in virtual space is accessed in user
Instruction synchronous, re-execution type
Power-On Reset
Manual Reset
CPU address error
4n + 3)
mode
Individual Exception Operations
Resets
General Exceptions
Rev. 3.00 Jan. 18, 2008 Page 227 of 1458
Section 7 Exception Handling
REJ09B0033-0300