HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 715

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

20.3.4
ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be
transferred, and confirms acknowledge bits to be received.
Bit
7
6
5
4
Bit Name
TIE
TEIE
RIE
NAKIE
I
2
C Bus Interrupt Enable Register (ICIER)
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables or
disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is disabled.
1: Transmit data empty interrupt request (TXI) is enabled.
Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt
(TEI) at the rising of the ninth clock while the TDRE bit in
ICSR is 1. TEI can be canceled by clearing the TEND bit
or the TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
Receive Interrupt Enable
This bit enables or disables the receive data full interrupt
request (RXI) when a receive data is transferred from
ICDRS to ICDRR and the RDRF bit in ICSR is set to 1.
RXI can be canceled by clearing the RDRF or RIE bit to
0.
0: Receive data full interrupt request (RXI) is disabled.
1: Receive data full interrupt request (RXI) is enabled.
NACK Receive Interrupt Enable
This bit enables or disables the NACK receive interrupt
request (NAKI) when the NACKF and AL bits in ICSR are
set to 1. NAKI can be canceled by clearing the NACKF,
OVE, or NAKIE bit to 0.
0: NACK receive interrupt request (NAKI) is disabled.
1: NACK receive interrupt request (NAKI) is enabled.
Rev. 3.00 Jan. 18, 2008 Page 653 of 1458
Section 20
I
2
C Bus Interface (IIC)
REJ09B0033-0300