HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 317

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

8.3.7
IRR3 is an 8-bit register that indicates whether interrupt requests from the RTC and SIM are
generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
Bit
7
6
5
4
3
2
Bit Name
TENDIR
TXIR
RXIR
ERIR

CUIR
Interrupt Request Register 3 (IRR3)
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R/W
Description
TENDI Interrupt Request
Indicates whether the TENDI (SIM) interrupt is
generated.
0: TENDI interrupt request is not generated
1: TENDI interrupt request is generated
TXI Interrupt Request
Indicates whether the TXI (SIM) interrupt request
is generated.
0: TXI interrupt request is not generated
1: TXI interrupt request is generated
RXI Interrupt Request
Indicates whether the RXI (SIM) interrupt request
is generated.
0: RXI interrupt request is not generated
1: RXI interrupt request is generated
ERI Interrupt Request
Indicates whether the ERI (SIM) interrupt request
is generated.
0: ERI interrupt request is not generated
1: ERI interrupt request is generated
Reserved
This bit is always read as 0. The write value should
always be 0.
CUI Interrupt Request
Indicates whether the CUI (RTC) interrupt request
is generated.
0: CUI interrupt request is not generated
1: CUI interrupt request is generated
Rev. 3.00 Jan. 18, 2008 Page 255 of 1458
Section 8
Interrupt Controller (INTC)
REJ09B0033-0300