HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 115

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
The little endian mode can also be specified as data format. Either big-endian or little-endian mode
can be selected according to the MD5 pin at reset. When MD5 is low at reset, the processor
operates in big-endian mode. When MD5 is high at reset, the processor operates in little-endian
mode. The endian mode cannot be modified dynamically.
In little endian mode, the MSB byte in the register corresponds to the highest address in the
memory, and the LSB the in the register corresponds to the lowest address (figure 2.8). For
example, if the contents of the general register R0 is stored at an address indicated by the general
register R1 in longword, the MSB byte of the R0 is stored at the address indicated by the (R1+3)
and the LSB byte of the R1 register is stored at the address indicated by the R1.
If the little endian mode is selected, the on-chip memory are accessed in little endian mode.
However, the on-chip device registers assigned to memory are accessed in big endian mode. Note
that the available access size (byte, word, or long word) differs in each register.
Note: The CPU instruction codes of this LSI must be stored in word units. In little endian mode,
Byte position
Byte position
in memory
in R0
the instruction code must be stored from lower byte to upper byte in this order from the
word boundary of the memory.
31
@(R1+3) @(R1+2) @(R1+1) @(R1+0)
Example: MOV.B R0, @R1
23
Figure 2.8
(a) Byte access
(R1 = Address 4n)
15
7
Data Format on Memory (Little Endian Mode)
[7:0]
[7:0]
0
@(R1+3) @(R1+2) @(R1+1) @(R1+0)
Example: MOV.W R0, @R1
(b) Word access
(R1 = Address 4n)
[15:8]
[15:8]
Rev. 3.00 Jan. 18, 2008 Page 53 of 1458
[7:0]
[7:0]
@(R1+3) @(R1+2) @(R1+1) @(R1+0)
[31:24]
[31:24]
Example: MOV.L R0, @R1
(c) Longword access
(R1 = Address 4n)
[23:16]
[23:16]
REJ09B0033-0300
Section 2
[15:8]
[15:8]
[7:0]
[7:0]
CPU

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