HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 264

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Cache
Note: W2LOAD and W3LOAD should not be set to 1 at the same time.
Rev. 3.00 Jan. 18, 2008 Page 202 of 1458
REJ09B0033-0300
Bit
31 to 17
16
15 to 10
9
8
7 to 2
1
0
Bit Name

LE

W3LOAD
W3LOCK

W2LOAD
W2LOCK
Initial
Value
All 0
0
All 0
0
0
All 0
0
0
R/W
R
R/W
R
R/W
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Lock enable (LE)
Controls cache lock mode.
0: Enters cache lock mode when the DSP bit in the SR
1: Enters cache lock mode regardless of the DSP bit
Reserved
These bits are always read as 0. The write value
should always be 0.
Way 3 Load (W3LOAD)
Way 3 Lock (W3LOCK)
When the cache is missed by a prefetch instruction
while in cache lock mode and when bits W3LOAD and
W3LOCK in CCR2 are set to 1, the data is always
loaded into way 3. Under any other condition, the
prefetched data is loaded into the way to which LRU
points.
Reserved
These bits are always read as 0. The write value
should always be 0.
Way 2 Load (W2LOAD)
Way 2 Lock (W2LOCK)
When the cache is missed by a prefetch instruction
while in cache lock mode and when bits W2LOAD and
W2LOCK in CCR2 are set to 1, the data is always
loaded into way 2. Under any other condition, the
prefetched data is loaded into the way to which LRU
points.
register is set to 1.
value.