HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 293

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

• Remarks
7.3.3
When the address translation unit of the memory management unit (MMU) is valid, MMU
exceptions are checked after a CPU address error has been checked. Four types of MMU
exceptions are defined: TLB miss exception, TLB invalid exception, TLB protection exception,
initial page write exception. These exceptions are checked in this order.
A vector offset for a TLB miss exception is defined as H'00000400 to simplify exception source
determination. For details on MMU exception operations, refer to section 4, Memory Management
Unit (MMU).
(1)
• Conditions
• Types
• Save address
• Exception code
• Remarks
• The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
An exception occurs when a DMA transfer is executed while an exception instruction address
described above is specified in the DMAC. Since the DMA transfer is performed
asynchronously with the CPU instruction operation, an exception is also requested
asynchronously with the instruction execution. For details on DMAC, refer to section 10,
Direct Memory Access Controller (DMAC).
Comparison of TLB addresses shows no address match.
Instruction synchronous, re-execution type
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
An exception occurred during read: H'040
An exception occurred during write: H'060
updated. The vector address for TLB miss exception is VBR + H'0400. To speed up TLB miss
processing, the offset differs from other exceptions.
TLB miss exception
General Exceptions (MMU Exceptions)
Rev. 3.00 Jan. 18, 2008 Page 231 of 1458
Section 7 Exception Handling
REJ09B0033-0300